Field Effect Transistors (FETs) have been a staple for low resistance electronic switches since their introduction to the market. In a common application a power FET or switch that is implemented using a FET is used to couple a supply voltage to a load at an output voltage terminal. Measuring the current flow through a FET is a common requirement by control circuits designed to keep the system (of which the FET and the control circuits are a part of) within its operational parameters, as well as especially as a safety to effect current limiting during high load conditions to prevent device damage or failure of the FET. The maximum current flow occurs in the conduction mode when the FET is on and the resistance between the drain and source (RDSon) is low. Traditional current sensing methods of adding a series resistor in the current path can generate a current measurement point, however this approach poses a tradeoff between power dissipation and peak measurement voltage. The series resistor value must be large enough for the sensed signal (a voltage corresponding to current through the resistor is measured) to be above the signal noise floor, yet as small as possible to reduce power dissipation. In addition, the power dissipation of the shunt resistor will be proportional to the square of the load current, hence negatively effecting the efficiency of the system. Furthermore, the parasitic inductance of such series resistance elements play an important detrimental role in determining circuit behavior when switching large currents in short time, causing voltage overshoots that overstress the circuits. Another known prior method is to use the voltage across parasitic resistance of an inductor, which is a part of the load, to approximate the load current.
FIG. 1 illustrates in a circuit diagram 100 another prior art circuit for estimating load current from a power FET. In FIG. 1, an example circuit 100 from U.S. Pat. No. 5,982,160 to Walters et al. is presented where the load current is approximated by reconstructing the voltage from a series inductor 110 across a resistor-capacitor (RC) network 120. The inductor 110 variation, which is attributed to the mechanical amount of wire used and the intrinsic temperature sensitivity, will have a noticeable effect on the sensing accuracy across a wide temperature range. In further work, as illustrated in FIG. 1 of U.S. Pat. No. 6,870,352 by Walters et. al., a temperature compensated resistor was used in the RC network 120 to help contain the temperature variance issue. Using such temperature compensated resistors is typically considerably more expensive than resistors integrated within the semiconductor package.
In the conduction mode, a FET has a somewhat linear RDSon which entices one to sense the voltage across the FET and use the appropriate RDSon value to estimate the approximate load current. However, the resistance RDSon could have a thermal coefficient as large as 8000 ppm/° C., equaling about 80% in a typical operating range of 25° C. to 125° C. To combat the large variance due to thermal changes, various arrangements of components with matching thermal coefficients (TC) have been employed to counteract the variations due to the intrinsic TC of the power FET.
FIG. 2 illustrates in another circuit diagram 200 another prior art solution for temperature compensated load current sensing. In FIG. 2, a schematic taken from FIG. 2 of U.S. Pat. No. 6,870,352 by Walters et al., shows the use of another thermally compensated sense resistor 220 (RSEN) is arranged and substantially matched to the thermal variation of the RDSon of power FET 210.
FIG. 3 illustrates another prior art load current sensing arrangement. In 300 a “current branch” methodology is employed to estimate the load current. The primary power FET 310 is switched by a PWM switching arrangement and as the load current flows through the load, part of the current is diverted to the sensing FET 330. Sense FET 330 is a smaller FET with a higher on resistance than the power FET 310. A sample of the load current will create a voltage Vs across resistor Rs that is proportional to the load current. Use of the sense FET 330 provides a simple method to approximate the load current, however it has a few drawbacks. Of concern is the achievable current accuracy and noise tolerance, which is limited by the voltage developed on the resistor. This also trades off with the ability to match the drain to source voltage of the two FETS; a mismatch is translated to nonlinearity in the current measurement. In addition, since the voltage across the resistor Rs is small in comparison to other methods, amplifier 332 is typically required to drive external (to the IC) loads, posing tradeoffs on the circuit response speed, range and accuracy.
In each of the prior solutions, temperature compensated resistors are needed with the best match available at the time of manufacture. These temperature compensated resistors are provided external to the integrated circuit of the FETs, and are quite expensive. Accordingly additional solutions have been attempted to exclude them.
FIG. 4 illustrates in another circuit schematic 400 an additional prior art current sensing topology excluding TC matched resistors. In FIG. 4, the power FET 410 is switched by a PWM switching circuit. The load current ILOAD flows through the load 490. Vin is typically a voltage higher than the breakdown voltage of the sensing circuitry. To protect the sensing circuits from the high voltage of Vin, another isolation FET 420 is used to block the high voltage when power FET 410 is in the off condition. When the power FET 410 is switched on, the voltage across it drops to a safe level, at which point the sensing switching circuitry will turn on the isolation FET 420 and turn off the protection FET 430. At this time voltage Vs is proportional to the on resistance RDSon of the power FET 410 and the current through it. The circuit has a fast following capability and also a reasonable V to I linearity at a given temperature. In addition, in a typical application, the peak sense voltage Vs could be in the range of 1 volt providing good range, resolution, and noise immunity compared to the few tens of mV in other architectures. Where this prior known arrangement falls short is in its nonlinearity due to temperature dependence of Rdson of FET 410, which can be a large value as was pointed out earlier. Temperature variation, which is also dependent on load applied, will produce a large variation even for a given current through the FET 410. In a complex system, there are methods of calibration to reduce the error, but that process in itself adds unwanted complexity and additional cost.
Continuing improvements are therefore desirable for methods and apparatus to provide current sensing in a power FET over a range of temperatures at a relatively low cost.